/* ____  _____             ____    ____    _                                 ______    _________   ____  _    *
* |_   \|_   _|           |_   \  /   _|  (_)                              .' ____ \  |  _   _  | |_   _|     *
*   |   \ | |    __   _     |   \/   |    __    .---.   _ .--.    .--.     | (___ \_| |_/ | | \_|   | |       *
*   | |\ \| |   [  | | |    | |\  /| |   [  |  / /'`\] [ `/'`\] / .'`\ \    _.____`.      | |       | |   _   *
*  _| |_\   |_   | \_/ |,  _| |_\/_| |_   | |  | \__.   | |     | \__. |   | \____) |    _| |_     _| |__/ |  *
* |_____|\____|  '.__.'_/ |_____||_____| [___] '.___.' [___]     '.__.'     \______.'   |_____|   |________|  *
*                                                                                                             *
* @file     IEC60730_CONTROL_PARAM.h                                                                          *
* @version  V3.00                                                                                             *
* $Revision: 8 $                                                                                             *
* $Date: 21/03/12 2:43p $                                                                                     *
* @brief    IEC60730 User Control Parameters                                                                  *
* @note                                                                                                       *
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.                                       *
***************************************************************************************************************/

#ifndef IEC60730_CONTROL_PARAM_H
#define IEC60730_CONTROL_PARAM_H

#include "stdint.h"
#include "sys.h"
#include "wdt.h"
#include "wwdt.h"
#include "etimer.h"
#include "rtc.h"
#include "i2s.h"
#include "gpio.h"
#include "nostdlib.h"

#define __ICCARM__

typedef void (*CLASSB_ERROR_HANDLING)(uint8_t);
typedef void (*CLASSB_WATCHDOG_RESET)(void);

/* Debug Message */
#define rt_printf	printf

/* ROM test parameters */
#ifdef __ARMCC_VERSION
extern uint32_t Image$$ABS_CheckSum$$Base;
extern uint32_t Image$$EXE_IROM2$$Base;
extern uint32_t Image$$RW_IRAM1$$Base;
extern uint32_t Image$$STACK_PTRN$$Base;

#define ROM_START               ((uint32_t *)&Image$$EXE_IROM2$$Base)
#define RAM_START               ((uint32_t *)&Image$$RW_IRAM1$$Base)
//#define STACK_START             ((uint32_t *)&Image$$STACK_PTRN$$Base)
//#define ROM_CHECKSUM            0x15ea4e
#define ROM_CHECKSUM            0x15f236
#endif

#ifdef __ICCARM__
// extern uint32_t ER_IROM1$$Base;
// extern uint32_t RW_IRAM1$$Base;
// extern uint32_t STACK_PTRN$$Base;
// #define ROM_START               ((uint32_t *)&EXE_IROM2$$Base)
// #define RAM_START               ((uint32_t *)&ER_IRAM1$$Base)
// //#define STACK_START             ((uint32_t *)&ER_STACK$$Base)
// //#define ROM_CHECKSUM            0x15ea4e
#define ROM_START               0x0008000
#define RAM_START               0x3C000000
#define ROM_CHECKSUM            0x15f236
#endif

#ifdef __ICCARM__
extern const uint32_t __Check_Sum;
extern uint32_t GOBAL_AREA$$Base;
extern uint32_t GOBAL_BACK_AREA$$Base;
#define GOBAL_VAR               (0x3C000000+0x2000)
#define GOBAL_BACK_VAR          (0x3C000000+0x3000)
#endif

#ifdef __ARMCC_VERSION
extern uint32_t Image$$GOBAL_AREA$$Base;
extern uint32_t Image$$GOBAL_BACK_AREA$$Base;
#define GOBAL_VAR               Image$$GOBAL_AREA$$Base
#define GOBAL_BACK_VAR          Image$$GOBAL_BACK_AREA$$Base
#endif



extern const uint32_t __Check_Sum;
#define ROM_END                 0x00300000
#define ROM_LENGTH              0x8000000       /* 128M */
#define CHECKSUM_SEED           0xFFFFFFFF

/*
Clock Ratio = (int)(HSCLOCK_FREQ/LSCLOCK_FREQ), MeanError = Clock RatioxClock_Devation, Valid Clock Ration =  Clock Ratio+/-MeanError */
#define HSCLOCK_FREQ        		100
#define LSCLOCK_FREQ        		10
#define CLOCK_DEVATION      		10

/* for Stack test */
#define STACK_SIZE              0x4000      // changeable
#define STACK_OVERRUN_PTRN0     0x12345432
#define STACK_OVERRUN_PTRN1     0x56789876
#define STACK_OVERRUN_PTRN2     0xfedc9876
#define STACK_OVERRUN_PTRN3     0xabcdef12

/* RAM test parameters */
#define NUC980_SRAM_SIZE        0x00004000

/*Safe State: 0 for IDLE STATE, 1 for RESET STATE*/
#define SAFE_STATE                  0

/* ADC test */
#define VREFF_H                     0xCCC   // 4095*(2.64/3.3)
#define VREFF_L                     0xA78   // 4095*(2.16/3.3)

#define ADC_PORT                    PB
#define VREFF_CHANNEL               8
#define MUX_CHANNEL                 0

/* each item test cycle */
#define CPUREG_TEST_CYCLE           3       // 3*test_cycle
#define PC_TEST_CYCLE               5       // 5*test_cycle
#define STACK_TEST_CYCLE            10
#define RAM_TEST_CYCLE              5
#define ROM_TEST_CYCLE              1
#define INT_TEST_CYCLE              30
#define ADC_TEST_CYCLE              4
#define MUX_TEST_CYCLE              4
#define GPIO_TEST_CYCLE             4
#define UART_TEST_CYCLE             100

#define REST_WDT_CYCLE              3
#define DRAM_TEST_CYCLE             5

/* RAM & ROM tested length each time */
#define RAM_RUNTIME_TEST_LENGTH     0x20    // based on Artisan SRAM achitecture
#define ROM_RUNTIME_TEST_LENGTH     0x20
#define DRAM_RUNTIME_TEST_LENGTH    0x10

/* for WDT test */
#define WDT_DURATION            700     // 0.7 sec per WDT interrupt

/* for Timer test */
#define TIMER0                 	0
#define TIMER1                  1
#define TIMER2                  2
#define TIMER3                  3
#define TIMER4                  4
#define TIMER5                  5

/* for Interrupt test */
#define	REG_RTC_CLKCTL  (RTC_BA+0x3C)       /*!< 32K Clock Control Register */

/* a. startup test */
#define TIMER1_STARTUP_FROM_32K             // Timer1 clock from 32K input
#define TIMER_DEVATION          20          // 20%
#define TIMER0_STARTUP_FREQ     1000        // Hz based (1 ms)
#define TIMER1_STARTUP_FREQ     100         // Hz based

/* b. runtime test */
#define TIMERY_RUNTIME_FROM_32K             // TimerY clock from 32K input
#define TIMERX                  TIMER0      // runtime based timer, can be changed
#define TIMERY                  TIMER5      // check with timer0, can be changed
#define IRQ_TIMERX              IRQ_TIMER0
#define IRQ_TIMERY              IRQ_TIMER5
#define	TIMERX_RUNTIME_FREQ     100         // 10 ms
#define	TIMERY_RUNTIME_FREQ     10       	// 100 ms

/* constant defined for judging each test item whether has been initialized or not */
#define RUNTIME_CPUREG_INIT         BIT0
#define RUNTIME_PC_INIT             BIT1
#define RUNTIME_STACK_INIT          BIT2
#define RUNTIME_INT_INIT            BIT3
#define RUNTIME_RAM_INIT            BIT4
#define RUNTIME_FLASH_INIT          BIT5
#define RUNTIME_DRAM_INIT           BIT6

//#define OPT_MEASURE_TIME

/* function declaration */
uint8_t CLASSB_STARTUP_TESTS(void);
void CLASSB_CHECK_RUNTIME_TESTS_EXECUTION(void);
void CLASSB_RUNTIME_TESTS(void);
void CLASSB_TESTLIB_INIT(CLASSB_ERROR_HANDLING, CLASSB_WATCHDOG_RESET);
void CLASSB_LSCLOCK_INT(void);
void CLASSB_HSCLOCK_INT(void);
uint32_t WriteGlobal(uint32_t *Addr, uint32_t value);
uint32_t ReadGlobal(uint32_t *Addr, uint32_t *value);


#endif  // IEC60730_CONTROL_PARAM_H
